This application claims the priority benefit of Taiwan application serial no. 90118123, filed Jul. 25, 2001.
1. Field of Invention
The present invention relates to a structure of a thin film transistor (TFT) array. More particularly, the present invention relates to a TFT array which has a dummy electrode connected to the last scanning line to compensate its capacitance. By the compensation of capacitance, the dummy electrode can get a balance in capacitance for the edge scanning line with the other usual scanning line.
2. Description of Related Art
Due to technologies of semiconductor fabrication and displaying device, the social environment with multimedia manner has also been greatly progressed. From the displaying device point of view, the cathode ray tube (CRT) has its economic advantages and has been widely used in the market of displaying device for the last years. However, if one considers the personal working environment associating with the terminal or display device, or looks at it from environment protection point of view which requires energy saving as a trend, the CRT has its issues about the size, weight, power consumption, and so on. So far, the CRT displaying device seems not able to solve those issues. Therefore, the TFT liquid crystal display (TFT-LCD) device with its advantages of high image quality, space utilizing efficiency, low power consumption, and no irradiation, has gradually been the new trend. The TFT-LCD generally uses liquid crystal that is filled between a substrate of TFT array and a color filter layer to form image pixels. In addition, an upper polarizer and a lower polarizer are formed as the outer layer, whereby an LCD panel is formed. Since the LCD panel by itself cannot produce light, a backlight module is incorporated with the LCD panel, so as to provide a light source for displaying image. The substrate of TFT array usually affects the displaying quality of the TFT-LCD device.
FIG. 1 is a drawing, illustrating the structure of TFT array for a conventional LCD device. FIG. 2 is a cross-sectional view, illustrating the structure of TFT array with respect to FIG. 1. The TFT array is formed on a substrate 100. There are several scanning lines 102a, 102b, 102c . . . and several data lines 104a, 104b, 104c, 104d, 104e, and so on. The adjacent two scanning lines, such as scanning lines 102a, 102b and two adjacent data lines 104a, 104b form an image pixel region. Each pixel region incorporates a TFT 106 and a pixel electrode 108 with respect to the TFT 106. Using the TFT 106 connected to the scanning line 102a as an example for descriptions, each of the TFT 106 has a gate electrode 106a, a source region 106b, and a drain region 106c. The gate electrode 106a of the TFT 106 is electrically connected to the scanning line 102a. The source region 106b of the TFT 106 is electrically connected to the data line 104a. The drain region 106c is electrically connected to the corresponding pixel electrode 108. More over, the pixel electrode 108 covers not only the pixel region but also the adjacent scanning line 102b, so as to form a storage capacitor Cst above the scanning line 102b. A similar capacitor Cst is also formed at the other scanning line 102c but the scanning line 102a has no capacitor Cst.
The scanning line 102b has the storage capacitor Cst. In addition, edge of each pixel electrode 108 corresponding to the scanning line 102b is also couple to the scanning line 102b to form a parasitic capacitor Cgs, and edge of the pixel electrode 108 is also coupled to the data line 104b to form a parasitic capacitor Csig1. The edge of the pixel electrode 108 is also coupled to the data line 104a to form a parasitic capacitor Csig2. Thus, the total capacitor Ctotal on the scanning line 102b is the equivalent to the liquid crystal capacitor CLC, parasitic capacitors Cgs, Csig1, Csig2, coupled in parallel and the storage capacitor Cst, coupled in cascade.
When data are written into the TFT 106 on the scanning lines 102a, 102b, 102c, the scanning lines 102a, 102b, 102c are sequentially applied with a voltage, so as to set the TFT to a xe2x80x9cONxe2x80x9d state under control of the scanning lines 102a, 102b, 102c. Then, the displaying information is written through the data lines 104a-104e into the TFT 106 under control of the scanning lines 102a, 102b, 102c. However, during the data writing-in process, the scanning line 102b and the scanning line 102c (not the edge scanning line) are covered by the adjacent pixel electrode to form the storage capacitor Cst and the liquid crystal capacitor CLC, but the edge scanning line 103a is not covered by any adjacent pixel electrode. As a result, the capacitive effect of the scanning line 102a is obviously different from that of the other scanning lines 102b, 102c. Due to this difference of capacitive effect between the scanning line 102a and the scanning lines 102b, 102c (not the edge scanning line), the driving condition on the scanning line 102a for the image pixels at the last row is not consistent with the other pixel rows.
FIG. 3A is a circuit configuration, illustrating the capacitor coupling structure for the scanning line other than the edge scanning line associating with the conventional TFT array. In FIG. 3A, the total capacitor Ctotal for the scanning line 102a and the scanning line 102b is equivalent to the liquid crystal capacitor CLC, parasitic capacitors Cgs, Csig1, Csig2, coupled in parallel and the storage capacitor Cst, coupled in cascade.
FIG. 3B is a circuit configuration, illustrating the equivalent capacitor for the scanning line other than the edge scanning line, associating with the conventional TFT array. In FIG. 3B, since the parasitic capacitors Cgs, Csig1, Csig2 are much smaller than the liquid crystal capacitor CLC, the equivalent capacitor after coupling in parallel is about equal to the liquid crystal capacitor CLC. Consequently, the total equivalent capacitor Ctotal is equal to the coupling of liquid crystal CLC with the storage capacitor Cst in cascade. However, for the structure of the conventional TFT array, since the edge scanning line has not been covered by the adjacent pixel electrode, it has no capacitor of storage capacitor Cst, parasitic capacitors Cgs, Csig1, Csig2, and the liquid crystal CLC. Since the capacitive effect is consistent between the edge scanning line 102a and the other scanning lines 102b, 102c, it causes that the displaying condition for the last row of pixel is consistent with the other scanning lines.
It is an object that the invention provides a structure of the TFT array, which includes a pixel electrode with capacitance compensation formed on the edge scanning line, so as to balance the capacitive effect on the edge scanning line to the other scanning lines.
As embodied and broadly described herein, the invention provides a structure of the TFT array which includes an additional row of pixel electrode coupled to the last scanning line for the last pixel electrode row. The last pixel electrode row has overlap with the last scanning line to form the equivalent storage capacitor. In addition, the liquid crystal exists on a portion of the pixel electrode row without overlapping with the last scanning line, resulting in the liquid crystal capacitor, which equivalent to the liquid crystal capacitor for the other scanning lines. The pixel electrode row can compensate the miss capacitance from the storage capacitor and the liquid crystal capacitor for the last scanning line. As a result, the difference of capacitive effect for the edge scanning line and the other scanning lines can be balanced, so as to improve the displaying quality.
The invention provides another structure of the TFT array which includes an additional row of pixel electrode coupled to the last scanning line for the last pixel electrode row. Moreover, the pixel electrode row is applied with a voltage. By adjusting the overlapping area between the pixel electrode row and the last scanning line, so as to have the equivalent capacitance equal to the total capacitance for the other scanning line. Thus, the displaying quality is effectively improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.